This invention relates to phase locked loop (PLL) circuits and more specifically to using a configurable time-sampled analog-value phase loop filter for the PLL.
A phase locked loop (PLL) is a circuit that generates an output signal whose phase is related to a phase of an input reference signal. In general, the circuit makes use of a feedback loop in which a signal representing a phase of the output signal is fed back and compared to the phase of the input reference signal. A circuit generates a signal representing a difference between the phases, and this signal drives a controlled oscillator that generates the output signal, thereby closing the feedback loop.
Referring to FIG. 1, an example of a PLL includes a phase comparator 110, which accepts a reference signal 105 and a feedback signal 145 and produces a phase difference signal 115. The phase difference signal is passed to a loop filter 120, which produces a control signal 125, which is passed to a controlled oscillator 130. The output 135 of the controlled oscillator 130 is passed back as the feedback signal 145 to the phase comparator 110, optionally first passing through a frequency divider 140, such that a division by a factor N results in the output signal having a frequency N times the frequency of the reference signal. In general, the loop filter 120 is used to adjust characteristics of the feedback loop, for instance, to control stability, response time, and/or steady-state error.
Referring to FIG. 2, in a more specific example of a Type II PLL circuit, a phase comparator 210 includes a phase frequency detector (PFD) 211 followed by a charge pump 214. The PFD 211 has two outputs, UP 212 and DOWN 213, whose timing is shown in FIG. 3. When the rising edge of the reference signal 105 leads the rising edge of the feedback signal 145, the UP pulse occurs for a greater duration than the DOWN pulse by the difference in the times of the rising edges, and when the rising edge of the feedback signal 145 leads the rising edge of the reference signal, the DOWN pulse occurs for a greater duration than the UP pulse, again by the difference in the times of the rising edges. The charge pump 214 produces a constant positive current during UP pulses and a constant negative current (of the same magnitude) during DOWN pulses. This results in an average current that is directly proportional to the phase error between the inputs to the PFD. The current output signal 215 of the charge pump is passed to a discrete component analog filter 220, for example, composed of a resistor and capacitor network, producing a voltage signal that is passed to a voltage controlled oscillator (VCO) 230. Characteristics of the PLL may be configured, in some cases be dynamically, according to one or more of the charge pump current level, the VCO gain, selection of analog component values in the filter, and the division factor of the feedback divider (if used).
Many PLLs have used external loop filters for high performance applications. PLL's having external loop filters can have a very low loop bandwidth, resulting in low phase noise specifications. A low loop bandwidth mitigates the phase noise profile caused by filter, charge pump, and PFD closer to the VCO output frequency. For VCOs running at GHz frequencies and VCO gain of 10's of MHz/V, charge pump currents in the 0.1 to 10 mA range this means values of capacitors for simple 2nd order filter for the PLL loop bandwidth of 10 KHz may require a range of 1 to 100 nF and zero setting resistor of 100 ohms. Integrating such large capacitor values on the die with PLL core is not feasible. Using external filters is thus accepted as a given and custom system design is generally required for most new variants of a system.
Another issue is that fractional signal multiplication and frequency synthesis (i.e., feedback division by a non-integer value of N) can suffer from spurious tones in the spectrum of the VCO output signal. This pathology can be mitigated by using higher order loop filters. This technique is complicated by the need for more sophisticated stability analysis of the loop then is usually required for the 2nd or 3rd order filter, constricting loop filter parameter choices and adding to the filter induced noise and the board area occupied by the filter. Consequently, integrating loop filter in the PLL core is considered to be even harder than in the case of integer clock multipliers and synthesizers.
Highly integrated systems on a chip (SOC) that boast both fully integrated clock generating PLLs and sometimes RF synthesizers, integrating PLL loop filter on silicon die have been available. Difficulties in design of such systems include forming large loop filter capacitors with low leakage current. Other approaches for integrating loop filters include digitizing the output of a phase detector and using a digital loop filter in what is referred to as an all-digital PLL, however use of digital filters can add complexity and introduce quantization noise induced error at the output of the phase detector.